MMC2107 Datasheet, PDF (402/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
the digital-to-analog converter (DAC) resistor-capacitor (RC) array and
a high-gain comparator.
The digital control section contains queue control logic to sequence the
conversion process and interrupt generation logic. Also included are the
periodic/interval timer, control and status registers, the conversion
command word (CCW) table, random-access memory (RAM), and the
result table RAM.
The bus interface unit (BIU) allows the QADC to operate with the
applications software through the IPbus environment.
18.3 Features
Features of the QADC module include:
• Internal sample and hold
• Up to eight analog input channels using internal multiplexing
• Directly supports up to four external multiplexers (for example, the
MC14051)
• Up to 18 total input channels with internal and external
multiplexing
• Programmable input sample time for various source impedances
• Two conversion command queues with a total of 64 entries
• Sub-queues possible using pause mechanism
• Queue complete and pause software interrupts available on both
queues
• Queue pointers indicate current location for each queue
• Automated queue modes initiated by:
– External edge trigger and gated trigger
– Periodic/interval timer, within QADC module [queues 1 and 2]
– Software command
• Single-scan or continuous-scan of queues
• 64 result registers
Technical Data
402
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA