MMC2107 Datasheet, PDF (580/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.14.13 Instruction Address FIFO Buffer (PC FIFO)
To ease debugging activity and keep track of program flow, a
first-in-first-out (FIFO) buffer stores the addresses of the last eight
instruction change-of-flow prefetches that were issued.
The FIFO is a circular buffer containing eight 32-bit registers and one
3-bit counter. All the registers have the same address, but any read
access to the FIFO address causes the counter to increment and point
to the next FIFO register. The registers are serially available to the
external command controller through the common FIFO address.
Figure 21-15 shows the structure of the PC FIFO.
INSTRUCTION FETCH ADDRESS
PC FIFO REGISTER 0
PC FIFO REGISTER 1
PC FIFO REGISTER 2
PC FIFO REGISTER 3
PC FIFO REGISTER 4
CIRCULAR
BUFFER
POINTER
PC FIFO REGISTER 5
PC FIFO REGISTER 6
Technical Data
580
PC FIFO REGISTER 7
PC FIFO SHIFT REGISTER
TCLK
TDO
Figure 21-15. OnCE PC FIFO
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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