MMC2107 Datasheet, PDF (549/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Boundary Scan
Table 21-3 defines the boundary-scan register.
• The first column shows bit numbers assigned to each of the
register’s cells. The bit nearest to TDO (the first to be shifted in) is
defined as bit 0.
• The second column lists the logical state bit for each MMC2107
pin alternately with the read/write direction control bit for that pin.
The logic state bits are non-inverting with respect to their
associated pins, so that a 1 logical state bit equates to a logical
high voltage on its corresponding pin. A direction control bit value
of 1 causes a pin’s logical state to be expressed by its logic state
bit, a read of a pin. A direction control bit value of 0 causes a pin’s
logical voltage to follow the state of its logical state bit, a write to a
pin.
Table 21-3. Boundary-Scan Register Definition (Sheet 1 of 4)
(Note: Shaded regions indicate optional pins)
Bit
Logical State and Direction
Control Bits for Each Pin
0 D31 logical state
1 D31 direction control
2 A12 logical state
3 A12 direction control
4 A13 logical state
5 A13 direction control
6 A14 logical state
7 A14 direction control
8 A15 logical state
9 A15 direction control
10 A16 logical state
11 A16 direction control
12 A17 logical state
13 A17 direction control
14 CLKOUT logical state
15 CLKOUT direction control
16 A18 logical state
Bit
Logical State and Direction
Control Bits for Each Pin
17 A18 direction control
18 A19 logical state
19 A19 direction control
20 RSTOUT logical state
21 RSTOUT direction control
22 A20 logical state
23 A20 direction control
24 RESET logical state
25 RESET direction control
26 A21 logical state
27 A21 direction control
28 A22 logical state
29 A22 direction control
30 TEA logical state
31 TEA direction control
32 EB0 logical state
33 EB0 direction control
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
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Go to: www.freescale.com
Technical Data
549