MMC2107 Datasheet, PDF (210/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
T3
S2
T1 T2
T6
S3
T4
RESET
S1
S4
T7
T8 T5
T9
S5
Figure 9-8. Program State Diagram
Table 9-7. Program Interlock State Descriptions
State
Mode
Next
State
Transition Requirement
Normal operation: Normal array reads and
S1
register accesses. Block protect information
and pulse width timing control can be
modified.
S2 T2 Write ERASE = 0 and SES = 1
S1 T1 Write SES = 0 or master reset
First program hardware interlock write:
Normal read operation. Array accepts
programming writes. Normal register
S2 accesses. CMFRCTL write cannot change
EHV. If write is to a register other than
CMFRMCR, no data is stored in program
page buffers; CMFR remains in S2.
Hardware interlock: Successful programming
write to any array location. Latches selected
data word into programming page buffer;
address latched to select location to
program. Bit that has been written remains
in program buffer until another write to it, or
S3 T3 SES is cleared, or a program margin read
determines bit needs no modification by
program operation. If write is to a register
(except CMFRMCR), no data is stored in
program page buffers, and CMFR remains
in S2. Writing to CMFRMCR does not allow
array to be programmed.
Technical Data
210
Non-Volatile Memory FLASH (CMFR)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA