MMC2107 Datasheet, PDF (138/618 Pages) –

Freescale Semiconductor, Inc.
Reset Controller Module
5.7.1.5 Loss of Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in
SYNCR is set and the PLL loses lock. The reset controller asserts
RSTOUT for approximately 512 cycles after the PLL has acquired lock.
The part then exits reset and begins operation.
5.7.1.6 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RESET pin
is negated and the PLL has acquired lock, the reset controller asserts
RSTOUT for approximately 512 cycles. Then the part exits reset and
begins operation.
5.7.2 Reset Control Flow
Figure 5-5 shows the reset logic control flow. In the flow description that
follows, there are references in parentheses to the control state box
numbers in the figure. All cycle counts given are approximate.
5.7.2.1 Synchronous Reset Requests
If either the external RESET pin is asserted by an external device for at
least four rising CLKOUT edges (3), or the watchdog timer times out, or
software requests a reset, the reset control logic latches the reset
request internally and enables the bus monitor (5). When the current bus
cycle is completed (6), RSTOUT is asserted (7). The reset control logic
waits until the RESET pin is negated (8) and for the PLL to attain lock
(9, 9A) before waiting 512 CLKOUT cycles (10). The reset control logic
may latch the configuration according to the RCON pin level (11, 11A)
before negating RSTOUT (12).
If the external RESET pin is asserted by an external device for at least
four rising CLKOUT edges during the 512 count (10) or during the wait
for PLL lock (9A), the reset flow switches to (8) and waits for the RESET
pin to be negated before continuing.
Technical Data
138
Reset Controller Module
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MMC2107 – Rev. 2.0
MOTOROLA