MMC2107 Datasheet, PDF (324/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.8.4.2 Gated Time Accumulation Mode
Setting the PAMOD bit configures the PA for gated time accumulation
operation. An active level on the PAI pin enables a divide-by-64 clock to
drive the PA. The PA edge bit, PEDGE, selects low levels or high levels
to enable the divided-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag,
PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to
generate interrupt requests.
NOTE:
The PAI input and timer channel 3 use the same pin. To use the PAI
input, disconnect it from the output logic by clearing the channel 3 output
mode and output level bits, OM3 and OL3. Also clear the channel 3
output compare mask bit, OC3M3.
The PA counter registers, TIMPACNTH/L reflect the number of pulses
from the divide-by-64 clock since the last reset.
NOTE: The timer prescaler generates the divide-by-64 clock. If the timer is not
active, there is no divide-by-64 clock.
PULSE
ACCUMULATOR
PAD
CHANNEL 3 OUTPUT COMPARE
OM3
OL3
OC3M3
Figure 15-26. Channel 3 Output Compare/Pulse Accumulator Logic
Technical Data
324
Timer Modules (TIM1 and TIM2)
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MMC2107 – Rev. 2.0
MOTOROLA