MMC2107 Datasheet, PDF (441/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
18.8.8 Result Registers
This subsection describes the result registers.
18.8.8.1 Right-Justified Unsigned Result Register
Address: 0x00ca_0280 through 0x00ca_02fe
Bit 15
14
13
12
11
10
9
Bit 8
Read: 0
0
0
0
0
0
Write:
RESULT
Reset: 0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
RESULT
Reset:
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-15. Right-Justified Unsigned Result Register (RJURR)
Read: Anytime except reads during stop mode are invalid
Write: Anytime except stop mode
RESULT[9:0] — Result Field
The conversion result is unsigned, right-justified data.
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
441