MMC2107 Datasheet, PDF (590/618 Pages) –

Freescale Semiconductor, Inc.
Electrical Specifications
22.8 PLL Electrical Specifications
Table 22-5. PLL Electrical Specifications
(V_DD and V_DDSYN = 2.7 to 3.6 V, V_SS = V_SSSYN = 0 V, T_A = T_L to T_H)
Parameter
Symbol
Min
Max
Unit
PLL reference frequency range
Crystal reference
External reference
1:1 mode
System frequency⁽¹⁾
External reference
On-chip PLL frequency
Loss of reference frequency⁽²⁾
Self-clocked mode frequency⁽³⁾
f_ref
f_sys
f_LOR
f_SCM
2
2
10
0
f_ref/64
100
0.5
10.0
33.0
MHz
33.0
33.0
MHz
33.0
250
kHz
15
MHz
EXTAL input high voltage
Crystal mode
All other modes (1:1, bypass, external)
V_IHEXT
V_DDSYN –1.0
V_DDSYN
V
2.0
V_DDSYN
EXTAL input low voltage
Crystal mode
All other modes (1:1, bypass, external)
PLL lock time^{(4), (5)}
Powerup-to-lock Time^{(4), (5)}
Without crystal reference
1:1 clock skew (between CLKOUT and EXTAL)⁽⁶⁾
Duty cycle of reference⁽⁴⁾
Frequency un-LOCK range
Frequency LOCK range
CLKOUT period jitter⁽⁷⁾
Measured at f_sys maximum
Peak-to-peak jitter (clock edge to clock edge)
Long-term jitter (averaged over 2-ms interval)
V_ILEXT
t_LPLL
t_LPLK
t_Skew
t_dc
f_UL
f_LCK
C_Jitter
V_SSSYN
V_SSSYN
—
—
–2
40
–1.5
–0.75
—
—
1.0
0.8
200
200
2
60
1.5
0.75
V
µs
µs
ns
% f_sys
% f_sys
% f_sys
5
0.01
% f_sys
1. All internal registers retain data at 0 Hz.
2. Loss of reference frequency is the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
3. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f_LOR with
default MFD/RFD settings.
4. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
5. Assuming a reference is available at power-up, lock time is measured from the time V_DD and V_DDSYN are valid to RSTOUT
negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal startup time must be added to
the PLL lock time to determine the total startup time.
6. PLL is operating in 1:1 PLL mode.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V_DDSYN and V_SSSYN and variation in crystal oscillator frequency increase the C_Jitter
percentage for a given interval.
Technical Data
590
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA