MMC2107 Datasheet, PDF (148/618 Pages) –

Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
The supervisor programming model consists of the user model plus 16
additional 32-bit general-purpose registers (R[15:0]’, or the alternate
file), the entire PSR, and a set of status/control registers (CR[12:0]).
Setting the S bit in the PSR enables supervisor mode operation.
The alternate file allows very low overhead context switching for
real-time event handling. While the alternate file is enabled,
general-purpose operands are accessed from it.
The vector base register (VBR) determines the base address of the
exception vector table. Exception shadow registers EPC and EPSR are
used to save the states of the program counter and PSR, respectively,
when an exception occurs. Shadow registers FPC and FPSR save the
states of the program counter and PSR, respectively, when an exception
occurs.
Scratch registers (SS[4:0]) are used to handle exception events.
The global control (GCR) and status (GSR) registers can be used for a
variety of system monitoring tasks.
The supervisor programming model includes the PSR, which contains
operation control and status information. In addition, a set of exception
shadow registers is provided to save the state of the PSR and the
program counter at the time an exception occurs. A separate set of
shadow registers is provided for fast interrupt support to minimize
context saving overhead.
Five scratch registers are provided for supervisor software use in
handling exception events. A single register is provided to alter the base
address of the exception vector table. Two registers are provided for
global control and status.
Technical Data
148
M•CORE M210 Central Processor Unit (CPU)
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MMC2107 – Rev. 2.0
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