MMC2107 Datasheet, PDF (460/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Situations S8 and S9 (Figure 18-30 and Figure 18-31) repeat the same
two situations with the RESUME bit set to a 1. When the RES bit is set,
following suspension, queue 2 resumes execution with the aborted
CCW, not the first CCW in the queue.
T1
T1
Q1: C1
C2
T2
PF1
Q2: C1 _C2
C3 C4
CF1
C2 C3 C4
RESUME=1
Q1
IDLE
ACTIVE
PAUSE
AACCTTIIVVEE
CF2
IDLE
Q2
IDLE
ACTIVE
SUSPEND
ACTIVE
IDLE
QS
0000
1000
0100
0110
1010
0010
0000
Figure 18-30. CCW Priority Situation 8
T1
T1
Q1: C1 C2
C3 C4
T2
Q2: _CC1 C2
PF1
C2
T2
C3 ^C4
CF1
C4
RESUME=1
Q1
IDLE
ACTIVE
PF2
PAUSE
ACTIVE
CF2
IDLE
Q2
IDLE
ACTIVE
SUSPEND ACT PAUSE ACTIVE
SUSPEND ACT
IDLE
QS
0000
0010
1010
0110 0101
0110
1010
0010
0000
Figure 18-31. CCW Priority Situation 9
Technical Data
460
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA