MMC2107 Datasheet, PDF (239/618 Pages) –

Freescale Semiconductor, Inc.
Clock Module
Functional Description
10.8.4.1 Alternate Clock Selection
Depending on which clock source fails, the loss-of-clock circuit switches
the system clocks source to the remaining operational clock. The
alternate clock source generates the system clocks until reset is
asserted. As Table 10-7 shows, if the reference fails, the PLL goes out
of lock and into self-clocked mode (SCM). The PLL remains in SCM until
the next reset. When the PLL is operating in SCM, the system frequency
depends on the value in the RFD field. The SCM system frequency
stated in electrical specifications assumes that the RFD has been
programmed to binary 000. If the loss-of-clock condition is due to PLL
failure, the PLL reference becomes the system clocks source until the
next reset, even if the PLL regains and relocks.
Table 10-7. Loss of Clock Summary
Clock
Mode
System Clock
Source
Before Failure
Reference Failure
Alternate Clock
Selected by LOC
Circuit⁽¹⁾ Until Reset
PLL Failure
Alternate Clock
Selected by
LOC Circuit
Until Reset
PLL
PLL
PLL self-clocked mode
PLL reference
External External clock
None
NA
1. The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 10-8.
A special loss-of-clock condition occurs when both the reference and the
PLL fail. The failures may be simultaneous, or the PLL may fail first. In
either case, the reference clock failure takes priority and the PLL
attempts to operate in SCM. If successful, the PLL remains in SCM until
the next reset. If the PLL cannot operate in SCM, the system remains
static until the next reset. Both the reference and the PLL must be
functioning properly to exit reset.
MMC2107 – Rev. 2.0
MOTOROLA
Clock Module
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Technical Data
239