MMC2107 Datasheet, PDF (315/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
15.7.15 Pulse Accumulator Control Register
Address: TIM1 — 0x00ce_0018
TIM2 — 0x00cf_0018
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
PAE PAMOD PEDGE CLK1 CLK0 PAOVI PAI
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-19. Pulse Accumulator Control Register (TIMPACTL)
Read: Anytime
Write: Anytime
PAE — Pulse Accumulator Enable Bit
PAE enables the pulse accumulator.
1 = Pulse accumulator enabled
0 = Pulse accumulator disabled
NOTE: The pulse accumulator can operate in event mode even when the timer
enable bit, TIMEN, is clear.
PAMOD — Pulse Accumulator Mode Bit
PAMOD selects event counter mode or gated time accumulation
mode.
1 = Gated time accumulation mode
0 = Event counter mode
PEDGE — Pulse Accumulator Edge Bit
PEDGE selects falling or rising edges on the PAI pin to increment the
counter.
In event counter mode (PAMOD = 0):
1 = Rising PAI edge increments counter
0 = Falling PAI edge increments counter
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
315