MMC2107 Datasheet, PDF (235/618 Pages) –

Freescale Semiconductor, Inc.
Clock Module
Functional Description
10.8 Functional Description
This subsection provides a functional description of the clock module.
10.8.1 System Clock Modes
The system clock source is determined during reset. The value of
V_DDSYN is latched during reset and is expected to remain at that state
after reset is negated. If V_DDSYN is changed during a reset other than
power-on reset, the internal clocks may glitch as the clock source is
changed between external clock mode and PLL clock mode. Whenever
V_DDSYN is changed in reset, an immediate loss of lock condition occurs.
Table 10-6 shows the clock-out frequency to clock-in frequency
relationships for the possible clock modes.
Table 10-6. Clock-Out and Clock-In Relationships
Clock Mode
Normal PLL clock mode
1:1 PLL clock mode
External clock mode
1. f_ref = input reference frequency
f_sys = CLKOUT frequency
MFD ranges from 0 to 7.
RFD ranges from 0 to 7.
PLL Options⁽¹⁾
f_sys = f_ref × (MFD + 2)/2^RFD
f_sys = f_ref
f_sys = f_ref/2
CAUTION: XTAL must be tied low in external clock mode when reset is asserted. If
it is not, clocks could be suspended indefinitely.
The external clock is divided by two internally to produce the system
clocks.
MMC2107 – Rev. 2.0
MOTOROLA
Clock Module
For More Information On This Product,
Go to: www.freescale.com
Technical Data
235