MMC2107 Datasheet, PDF (410/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Table 18-2. QADC Memory Map
Address
MSB
LSB _Access⁽¹⁾
0x00ca_0000
QADC module configuration register (QADCMCR)
S
0x00ca_0002
QADC test register (QADCTEST)⁽²⁾
S
0x00ca_0004
Reserved⁽³⁾
—
0x00ca_0006
Port QA data register (PORTQA) Port QB data register (PORTQB)
S/U
0x00ca_0008
Port QA data direction register (DDRQA)
S/U
0x00ca_000a
QADC control register 0 (QACR0)
S/U
0x00ca_000c
QADC control register 1 (QACR1)
S/U
0x00ca_000e
QADC control register 2 (QACR2)
S/U
0x00ca_0010
QADC status register 0 (QASR0)
S/U
0x00ca_0012
QADC status register 1 (QASR1)
S/U
0x00ca_0014–
0x00ca_01fe
Reserved⁽³⁾
—
0x00ca_0200–
0x00ca_027e
Conversion command word table (CCW)
S/U
0x00ca_0280–
0x00ca_02fe
Right justified, unsigned result register (RJURR)
S/U
0x00ca_0300–
0x00ca_037e
Left justified, signed result register (LJSRR)
S/U
0x00ca_0380–
0x00ca_03fe
Left justified, unsigned result register (LJURR)
S/U
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
only addresses have no effect and result in a cycle termination transfer error.
2. Access results in the module generating an access termination transfer error if not in test mode.
3. Read/writes have no effect and the access terminates with a transfer error exception.
Technical Data
410
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
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