MMC2107 Datasheet, PDF (73/618 Pages) –

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address
0x00c8_0004
0x00c8_0005
0x00c9_0004
0x00c9_0005
0x00c8_0006
↓
0x00c8_0007
0x00ca_0008
↓
0x00ca_ffff
Register Name
Bit Number
Bit 15
14
13
12
11
10
9
Bit 8
PIT Count Register Read: PC15 PC14 PC13 PC12 PC11 PC10
PC9
PC8
(PCNTR)
See page 289.
Write:
Reset: 1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
Read: PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Write:
Reset: 1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
Access results in the module generating an access termination transfer error.
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
Access results in a bus monitor timeout generating an access termination transfer error.
Queued Analog-to-Digital Converter (QADC)
Bit 15
14
13
12
11
10
9
Bit 8
0x00ca_0000
QADC Module Read:
0
0
0
0
0
0
0x00ca_0001
Configuration Register
QSTOP
(QADCMCR) ^Write:
QDBG
See page 411. Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
SUPV
Write:
Reset: 1
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0x00ca_0002
0x00ca_0003
QADC Test Register
(QADCTEST)
See page 412.
Access results in the module generating an access termination transfer error if not in test mode.
Bit 7
6
5
4
3
2
1
Bit 0
Access results in the module generating an access termination transfer error if not in test mode.
P = Current pin state
U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 20 of 34)
MMC2107 – Rev. 2.0
MOTOROLA
System Memory Map
For More Information On This Product,
Go to: www.freescale.com
Technical Data
73