MMC2107 Datasheet, PDF (207/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
Functional Description
Blocks of the CMFR that are protected (PROTECT[block] = 1) are not
programmed.
The program sequence is outlined in 9.8.4.1 Program Sequence and
depicted in the flowchart form in Figure 9-7.
9.8.4.1 Program Sequence
Use this sequence to enable the high voltage to the array or shadow
information for program operation:
1. Make sure the CMFRMTR and CMFRCTL are in their reset states.
2. Set PAWS[2] = 1 and GDB = 1 in CMFRMTR.
3. In CMFRMCR, write PROTECT[7:0] to disable protection of
blocks to be programmed.
4. Use the procedure in Table 9-6 to write the pulse width timing
control fields for a program pulse.
5. In CMFRCTL, clear the ERASE bit, and write BLOCK[7:0] to
select the array blocks to be programmed.
6. In CMFRCTL, set the SES bit.
7. Programming write — A successful write to the array locations to
be programmed. This updates the programming page buffer(s)
with the information to be programmed. All accesses to the array
after the first write are to the same block offset address regardless
of the address provided. Thus the locations accessed after the first
programming write are limited to the page locations to be
programmed. Off-page read accesses of the array after the first
programming write are program margin reads.
NOTE:
All program page buffers share the same block offset address stored in
the BIU. The block offset address is extracted from the address of the
first programming write. To select the array block(s) to be programmed,
the program page buffers use BLOCK[7:0]. Subsequent writes fill in the
programming page buffers using the block address to select the program
page buffer and the page word address to select the word in the page
buffer.
MMC2107 – Rev. 2.0
MOTOROLA
Non-Volatile Memory FLASH (CMFR)
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Technical Data
207