MMC2107 Datasheet, PDF (418/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
PSA — Prescaler Add Clock Tick Bit
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
PSL[2:0] — Prescaler Clock Low Time Field
The PSL field selects the QCLK low time in the prescaler.
See Section 22. Electrical Specifications for f_QCLK values.
To keep the QCLK within the specified range, the PSL field selects the
low time of the QCLK, which can range from one to eight system clock
cycles. The minimum low time for the clock is specified as t_PSL.
Table 18-4 displays the bits in PSL field which enable a range of
QCLK low times.
Table 18-4. Prescaler Clock Low Times
PSL[2:0]
000
001
010
011
100
101
110
111
QCLK Low Time
1 system clock cycle
2 system clock cycles
3 system clock cycles
4 system clock cycles
5 system clock cycles
6 system clock cycles
7 system clock cycles
8 system clock cycles
Technical Data
418
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
MOTOROLA