MMC2107 Datasheet, PDF (35/618 Pages) –

Freescale Semiconductor, Inc.
List of Figures
MMC2107 – Rev. 2.0
MOTOROLA
Figure
Title
Page
18-49
18-50
18-51
18-52
18-53
18-54
Gated Mode, Continuous Scan Timing . . . . . . . . . . . . . . . 491
Star-Ground at the Point of Power Supply Origin. . . . . . . . 493
Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . . 494
Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . 494
External Multiplexing of Analog Signal Sources. . . . . . . . .496
Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . 497
19-1
19-2
19-3
19-4
19-5
19-6
Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Master Mode — 1-Clock Read and Write Cycle. . . . . . . . .515
Master Mode — 2-Clock Read and Write Cycle. . . . . . . . .515
Internal (Show) Cycle Followed . . . . . . . . . . . . . . . . . . . . . . . .
by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
Internal (Show) Cycle Followed
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
20-1 Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 523
20-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
20-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
20-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
20-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
Top-Level Tap Module and Low-Level (OnCE)
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Top-Level TAP Controller State Machine . . . . . . . . . . . . . .540
IDCODE Register Bit Specification . . . . . . . . . . . . . . . . . .545
OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Low-Level (OnCE) Tap Module Data Registers (DRs). . . . 554
OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . . 559
OnCE Command Register (OCMR) . . . . . . . . . . . . . . . . . . 562
OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . . 564
OnCE Status Register (OSR) . . . . . . . . . . . . . . . . . . . . . . .568
OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . 570
OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . . 576
List of Figures
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Technical Data
35