MMC2107 Datasheet, PDF (539/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Top-Level Test Access Port (TAP)
NOTE:
As an input, this signal provides multiple functions such as:
• The main function is a means of entering debug mode from an
external command controller. This signal, when asserted, causes
the CPU to finish the current instruction being executed, save the
instruction pipeline information, enter debug mode, and wait for
commands to be entered from the serial debug input line. This
input must be asserted for at least three system clocks, sampled
with the rising CLKOUT edge. This function is ignored during
reset. While the processor is in debug mode, this signal is still
sampled but has no effect until debug mode is exited.
• Another input function is to enable OnCE. This is an alternate
method to the ENABLE_MCU_ONCE JTAG command to enable
the OnCE logic to be accessible via the JTAG interface. This input
signal must be asserted low (while in the test-logic-reset state with
POR/TRST not asserted) for at least two TCLK rising edges. Once
enabled, the OnCE will remain enabled until the next POR or
TRST resets.
• Another input function is as a wake-up event from a low-power
mode of operation. Asynchronously asserting this signal will cause
the clock controller to restart. This signal must be held asserted
until the M•CORE receives three valid rising edges on the system
clock. Then the processor will exit the low-power mode and go into
debug mode.
If used to enter debug mode, DE must be pulled negated before the
processor exits debug mode to prevent a still low signal from being
unintentionally recognized as another debug request. Also, asserting
this signal to enter debug mode may prevent external logic from seeing
the processor output acknowledgment since the external pullup may not
be able to pull the signal negated before the handshake is asserted.
Finally, if using this signal to enable OnCE outside of reset it may be
seen as a request to enter debug mode.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
For More Information On This Product,
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Technical Data
539