MMC2107 Datasheet, PDF (156/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
7.7.1 Memory Map
Table 7-1. Interrupt Controller Module Memory Map
Address
Bits 31–24
Bits 23–16
Bits 15–8
Bits 7–0
Access⁽¹⁾
0x00c5_0000
Interrupt control register (ICR)
Interrupt status register (ISR)
S/U
0x00c5_0004
Interrupt force register high (IFRH)
S/U
0x00c5_0008
IInterrupt force register low (IFRL)
S/U
0x00c5_000c
Interrupt pending register (IPR)
S/U
0x00c5_0010
Normal interrupt enable register (NIER)
S/U
0x00c5_0014
Normal interrupt pending register (NIPR)
S/U
0x00c5_0018
Fast interrupt enable register (FIER)
S/U
0x00c5_001c
Fast interrupt pending register (FIPR)
S/U
0x00c5_0020
through
Unimplemented⁽²⁾
—
0x00c5_003c
Priority level select registers (PLSR0–PLSR39)
0x00c5_0040
PLSR0
PLSR1
PLSR2
PLSR3
S
0x00c5_0044
PLSR4
PLSR5
PLSR6
PLSR7
S
0x00c5_0048
PLSR8
PLSR9
PLSR10
PLSR11
S
0x00c5_004c
PLSR12
PLSR13
PLSR14
PLSR15
S
0x00c5_0050
PLSR16
PLSR17
PLSR18
PLSR19
S
0x00c5_0054
PLSR20
PLSR21
PLSR22
PLSR23
S
0x00c5_0058
PLSR24
PLSR25
PLSR26
PLSR27
S
0x00c5_005c
PLSR28
PLSR29
PLSR30
PLSR31
S
0x00c5_0060
PLSR32
PLSR33
PLSR34
PLSR35
S
0x00c5_0064
PLSR36
PLSR37
PLSR38
PLSR39
S
0x00c5_0068
through
Unimplemented⁽²⁾
—
0x00c5_007c
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
only addresses have no effect and result in a cycle termination transfer error.
2. Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
Technical Data
156
Interrupt Controller Module
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA