MMC2107 Datasheet, PDF (442/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
18.8.8.2 Left-Justified Signed Result Register
Address: 0x00ca_0300 through 0x00ca_037e
Bit 15
14
13
12
11
10
9
Bit 8
Read:
S
Write:
RESULT
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
RESULT
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-16. Left-Justified Signed Result Register (LJSRR)
S — Sign Bit
RESULT[14:6] — Result Field
The conversion result is signed, left-justified data.
18.8.8.3 Left-Justified Unsigned Result Register
Address: 0x00ca_0380 through 0x00ca_03fe
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Write:
RESULT
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
RESULT
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-17. Left-Justified Unsigned Result Register (LJURR)
RESULT[15:6] — Result Field
The conversion result is unsigned, left-justified data.
Technical Data
442
Queued Analog-to-Digital Converter (QADC)
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Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA