MMC2107 Datasheet, PDF (568/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.14.4.3 OnCE Status Register
The 16-bit OnCE status register (OSR) indicates the reason(s) that
debug mode was entered and the current operating mode of the CPU.
Bit 15
14
13
12
11
10
9
Bit 8
Read: 0
0
0
0
0
0
HDRO DRO
Write:
Reset:
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read: MBO
SWO
TO
FRZO SQB
SQA
PM1
PM0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 21-10. OnCE Status Register (OSR)
HDRO — Hardware Debug Request Occurrence Flag
HDRO is set when the processor enters debug mode as a result of a
hardware debug request from the IDR signal or the DE pin. This bit is
cleared on test logic reset or when debug mode is exited with the GO
and EX bits set.
DRO — Debug Request Occurrence Flag
DRO is set when the processor enters debug mode and the debug
request (DR) control bit in the OnCE control register is set. This bit is
cleared on test logic reset or when debug mode is exited with the GO
and EX bits set.
MBO — Memory Breakpoint Occurrence Flag
MBO is set when a memory breakpoint request has been issued to
the CPU via the BRKRQ input and the CPU enters debug mode. In
some situations involving breakpoint requests on instruction
prefetches, the CPU may discard the request along with the prefetch.
In this case, this bit may become set due to the CPU entering debug
mode for another reason. This bit is cleared on test logic reset or
when debug mode is exited with the GO and EX bits set.
Technical Data
568
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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