MMC2107 Datasheet, PDF (228/618 Pages) –

Clock Module
Freescale Semiconductor, Inc.
MFD[2:0] — Multiplication Factor Divider Field
MFD[2:0] contain the binary value of the divider in the PLL feedback
loop. See Table 10-3. The MFD[2:0] value is the multiplication factor
applied to the reference frequency. When MFD[2:0] are changed or
the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL
mode, MFD[2:0] are ignored, and the multiplication factor is one.
NOTE: In external clock mode, the MFD[2:0] bits have no effect.
See Table 10-6.
Table 10-3. System Frequency Multiplier of the Reference
Frequency⁽¹⁾ in Normal PLL Mode
000 001
(2x) (3x)
000 (÷ 1)
2
3
001 (÷ 2)⁽²⁾
1
3/2
010 (÷ 4)
1/2 3/4
011 (÷ 8)
1/4 3/8
100 (÷ 16)
1/8 3/16
101 (÷ 32) 1/16 3/32
110 (÷ 64) 1/32 3/64
111 (÷ 128) 1/64 3/128
1. f_sys = f_ref x (MFD + 2)/2^RFD
2. Default value out of reset
010
(4x)
4
2
1
1/2
1/4
1/8
1/16
1/32
MFD[2:0]
011 100
(5x) (6x)
5
6
5/2
3
5/4 3/2
5/8 3/4
5/16 3/8
5/32 3/16
5/64 3/32
5/128 3/64
101
(7x)
7
7/2
7/4
7/8
7/16
7/32
7/64
7/128
110 111
(8x) (9x)
8
9
4
9/2
2
9/4
1
9/8
1/2 9/16
1/4 9/32
1/8 9/64
1/16 9/128
LOCRE — Loss of Clock Reset Enable Bit
The LOCRE bit determines how the system handles a loss of clock
condition. When the LOCEN bit is clear, LOCRE has no effect. If the
LOCS flag in SYNSR indicates a loss of clock condition, setting the
LOCRE bit causes an immediate reset. To prevent an immediate
reset, the LOCRE bit must be cleared before entering stop mode with
the PLL disabled.
1 = Reset on loss of clock
0 = No reset on loss of clock
NOTE: In external clock mode, the LOCRE bit has no effect.
Technical Data
228
Clock Module
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MMC2107 – Rev. 2.0
MOTOROLA