MMC2107 Datasheet, PDF (386/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
17.8 Functional Description
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
Setting the SPE bit in SPICR1 enables the SPI and dedicates four SPI
port pins to SPI functions:
• Slave select (SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
When the SPE bit is clear, the SS, SCK, MOSI, and MISO pins are
general-purpose I/O pins controlled by SPIDDR.
The 8-bit shift register in a master SPI is linked by the MOSI and MISO
pins to the 8-bit shift register in the slave. The linked shift registers form
a distributed 16-bit register. In an SPI transmission, the SCK clock from
the master shifts the data in the 16-bit register eight bit positions, and the
master and slave exchange data. Data written to the master SPIDR
register is the output data to the slave. After the exchange, data read
from the master SPIDR is the input data from the slave.
SPIDR
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER SPI
MISO
MOSI
SCK
SS
V_DD
MISO
MOSI
SCK
SS
SPIDR
SHIFT REGISTER
SLAVE SPI
Figure 17-10. Full-Duplex Operation
Technical Data
386
Serial Peripheral Interface Module (SPI)
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MMC2107 – Rev. 2.0
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