MMC2107 Datasheet, PDF (392/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Technical Data
392
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI PIN
CHANGE O
MISO PIN
SS PIN (I)
SPI CLOCK
SS SYNCHRONIZED
TO SPI CLOCK
MISO PIN
SPIDR WRITE
THIS CYCLE
Figure 17-13. Transmission Error Due to Master/Slave Clock Skew
The synchronized SS signal is synchronized to the SPI clock.
Figure 17-13 shows an example with the synchronized SS signal almost
a full SPI clock cycle late. While the synchronized SS of the slave is high,
writing is allowed even though the SS pin is already low. The write can
change the MISO pin while the master is sampling the MISO line. The
first bit of the transfer may not be stable when the master samples it, so
the byte sent to the master may be corrupted.
Also, if the slave generates a late write, its state machine may not have
time to reset, causing it to incorrectly receive a byte from the master.
This error is most likely when the SCK frequency is half the slave SPI
clock frequency. At other baud rates, the SCK skew is no more than one
SPI clock, and there is more time between the synchronized SS signal
and the first SCK edge. For example, with a SCK frequency one-fourth
Serial Peripheral Interface Module (SPI)
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MMC2107 – Rev. 2.0
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