MMC2107 Datasheet, PDF (182/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
9.4 Modes of Operation
This subsection describes the two modes of operation:
1. Stop mode
2. Disabled mode
9.4.1 Stop Mode
When the FSTOP bit in the CMFR module configuration register
(CMFRMCR) register is set, the CMFR enters a low-power operation
mode. Write to FSTOP bit is allowed only when SES = 0 in the CMFR
high-voltage control register (no high-voltage operations). When the
FSTOP bit is set, only CMFRMCR can be accessed, accesses to the
array are ignored, and accesses to other registers are terminated with
bus errors. To prevent unpredictable behavior it is recommended to
change this bit separately. The CMFR requires a recovery time of 16
clocks after exiting stop mode. This means that if a read access to the
array is done immediately after writing FSTOP = 0, the access is
completed after 16 clocks.
9.4.2 Disabled Mode
When the DIS bit in CMFRMCR is set, the array is disabled and the BIU
does not respond to array accesses. Write to DIS bit is allowed only
when SES = 0 (no high-voltage operations). Disabling the CMFR does
not place the module in the lowest power consumption mode like stop
mode, but does place the CMFR in a safe state and prevents the CMFR
from conflicting on the internal bus during an external boot. There is no
recovery time required when re-enabling the CMFR.
For details of the CMFR module configuration register (CMFRMCR) see
9.7.1.1 CMFR Module Configuration Register and 9.7.1.3 CMFR
High-Voltage Control Register.
Technical Data
182
Non-Volatile Memory FLASH (CMFR)
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MMC2107 – Rev. 2.0
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