MMC2107 Datasheet, PDF (81/618 Pages) –

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address
Register Name
Bit Number
Timer 1 (TIM1) and Timer 2 (TIM2)
Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 are at 0x00cf_####.
Bit 7
6
5
4
3
Timer Input Capture/ Read: 0
0
0
0
0x00ce_0000
0x00cf_0000
Output Compare Select
Register (TIMIOS)
Write:
IOS3
See page 300. Reset: 0
0
0
0
0
Bit 7
6
5
4
3
0x00ce_0001
0x00cf_0001
Timer Compare Force
Register (TIMCFORC)
See page 301.
Read:
Write:
0
0
0
0
0
FOC3
Reset: 0
0
0
0
0
Bit 7
6
5
4
3
Timer Output Compare 3 Read: 0
0
0
0
0x00ce_0002
0x00cf_0002
Mask Register
(TIMOC3M)
Write:
OC3M3
See page 302. Reset: 0
0
0
0
0
Bit 7
6
5
4
3
Read: 0
0
0
0
0x00ce_0003
0x00cf_0003
Timer Output Compare 3
Data Register (TIMOC3D) Write:
See page 303. _Reset:
0
0
0
OC3D3
0
0
Bit 7
6
5
4
3
0x00ce_0004
0x00cf_0004
Timer Counter Register
High (TIMCNTH)
See page 304.
Read:
Write:
Reset:
Bit 15
0
14
0
13
0
12
0
11
0
Bit 7
6
5
4
3
0x00ce_0005
0x00cf_0005
Timer Counter Register ^{Read: Bit 7}
Low (TIMCNTL) Write:
See page 304.
6
5
4
3
Reset: 0
0
0
0
0
Bit 7
6
5
4
3
0x00ce_0006
0x00cf_0006
Timer System Control
Register 1 (TIMSCR1)
See page 305.
Read:
Write:
TIMEN
0
Reset: 0
0
0
0
TFFCA
0
0
0
2
IOS2
0
2
0
FOC2
0
2
OC3M2
0
2
OC3D2
0
2
10
0
2
2
0
2
0
0
1
IOS1
0
1
0
FOC1
0
1
OC3M1
0
1
OC3D1
0
1
9
0
1
1
0
1
0
0
Bit 0
IOS0
0
Bit 0
0
FOC0
0
Bit 0
OC3M0
0
Bit 0
OC3D0
0
Bit 0
Bit 8
0
Bit 0
Bit 0
0
Bit 0
0
0
P = Current pin state
U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 28 of 34)
MMC2107 – Rev. 2.0
MOTOROLA
System Memory Map
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Technical Data
81