MMC2107 Datasheet, PDF (516/618 Pages) –

Freescale Semiconductor, Inc.
External Bus Interface Module (EBI)
19.8 Bus Exception Operation
19.8.1 Transfer Error Termination
Normal bus cycle termination requires the assertion of the TA pin or the
internal transfer acknowledge signal. Minimal bus exception support is
provided by transfer error cycle termination. For transfer error cycle
termination, the external TEA pin or the internal transfer error
acknowledge signal is asserted. Transfer error cycle termination takes
precedence over normal cycle termination, provided TEA assertion
meets its timing constraints.
The internal bus monitor will assert the internal transfer error
acknowledge signal when TA response time is too long.
19.8.2 Transfer Abort Termination
External bus cycles which are aborted by the M•CORE, still have the
address, R/W, TC[2:0], TSIZ[1:0], CS (if used), OE (reads only), and
SHS (if used) driven to the external pins.
19.9 Emulation Support
19.9.1 Emulation Chip-Selects (CSE[1:0])
While in emulation mode or master mode, special emulator chip-selects
(CSE[1:0]) are driven externally to allow internal/external accesses to be
tracked by external hardware See Table 19-4.
In emulation mode, all port registers are mapped externally.
CSE[1:0] = 10 whenever any emulated port registers are addressed.
The lower bits of the address bus indicate the register accessed within
the block.
Accesses to the address space which contains the registers for the
internal modules (except ports) are indicated by CSE[1:0] = 11.
Internal accesses, other than to the specific module control registers, are
indicated by CSE[1:0] = 01. To emulate internal FLASH, the external
Technical Data
516
External Bus Interface Module (EBI)
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MMC2107 – Rev. 2.0
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