MMC2107 Datasheet, PDF (419/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
18.8.5.2 Control Register 1
Control register 1 (QACR1) is the mode control register for the operation
of queue 1. The applications software defines the queue operating mode
for the queue and may enable a completion and/or pause interrupt. Most
of the bits are typically written once when the software initializes the
QADC and not changed afterward.
Stop mode resets the register ($0000)
Address: 0x00ca_000c and 0x00ca_000d
Bit 15
14
13
12
11
10
9
Bit 8
Read:
0
CIE1
PIE1
MQ112 MQ111 MQ110 MQ19 MQ18
Write:
SSE1
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-9. QADC Control Register 1 (QACR1)
Read: Anytime
Write: Anytime except stop mode
CIE1 — Queue 1 Completion Interrupt Enable Bit
CIE1 enables an interrupt upon completion of queue 1. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 1.
1 = Enable interrupt after the conversion of the sample requested
by the last CCW in queue 1
0 = Disable queue 1 completion interrupt
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
419