MMC2107 Datasheet, PDF (249/618 Pages) –

11.3 Signals
Freescale Semiconductor, Inc.
Ports Module
Signals
See Table 11-3 in 11.5 Functional Description for signal location and
naming convention.
11.4 Memory Map and Registers
The ports programming model consists of these registers:
• The port output data registers (PORTx) store the data to be driven
on the corresponding port pins when the pins are configured for
digital output.
• The port data direction registers (DDRx) control the direction of
the port pin drivers when the pins are configured for digital I/O.
• Port pin data/set data registers (PORTxP/SETx):
– Reflect the current state of the port pins
– Allow for setting individual bits in PORTx
• The port clear output data registers (CLRx) allow for clearing
individual bits in PORTx.
• The port pin assignment registers (PCDPAR and PEPAR) control
the function of each pin of the C, D, E, I7, and I6 ports.
In emulation mode, accesses to the port registers are ignored and the
port access goes external so that emulation hardware can satisfy the
port access request. The cycle termination is always provided by the port
logic, even in emulation mode.
All port registers are word-, half-word, and byte-accessible and are
grouped to allow coherent access to port data register groups. Writing to
reserved bits in the port registers has no effect and reading returns 0s.
The I/O ports have a base address of 0x00c0_0000.
MMC2107 – Rev. 2.0
MOTOROLA
Ports Module
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Technical Data
249