MMC2107 Datasheet, PDF (230/618 Pages) –

Clock Module
Freescale Semiconductor, Inc.
STPMD[1:0] — Stop Mode Bits
STPMD[1:0] control PLL and CLKOUT operation in stop mode as
shown in Table 10-4.
Table 10-4. STPMD[1:0] Operation in Stop Mode
STPMD[1:0]
00
01
10
11
System
Clocks
Disabled
Disabled
Disabled
Disabled
Operation During Stop Mode
PLL
OSC
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
CLKOUT
Enabled
Disabled
Disabled
Disabled
RSVD4, RSVD1, and RSVD0 — Reserved
Writing to these read/write bits updates their values but has no effect
on functionality.
10.7.2.2 Synthesizer Status Register
The synthesizer status register (SYNSR) is a read-only register that can
be read at any time. Writing to the SYNSR has no effect and terminates
the cycle normally.
Address: 0x00c3_0002
Bit 7
6
5
4
3
2
1
Bit 0
Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS
0
0
Write:
Reset: Note 1 Note 1 Note 1 Note 2 Note 2
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Notes:
1. Reset state determined during reset configuration.
2. See the LOCKS and LOCK bit descriptions.
Figure 10-3. Synthesizer Status Register (SYNSR)
Technical Data
230
Clock Module
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MMC2107 – Rev. 2.0
MOTOROLA