MMC2107 Datasheet, PDF (198/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
Table 9-4. System Clock Range
SCLKR[2:0]
System Clock Frequency (MHz)
Minimum
Maximum⁽¹⁾
Clock Scaling (R)
000
Reserved
001
8
12
1
010
12
18
3/2
011
18
24
2
100
24
36
3
101
36
40
4
110 and 111
Reserved by Motorola for future use
1. The maximum system clock frequency is 33 MHz.
The control of the program/erase pulse timing is divided into three
functions.
The first term of the timing control is the clock scaling, R. The value of R
is determined by the system clock range (SCLKR[2:0]). SCLKR[2:0]
defines the base clock of the pulse timer. Use Table 9-4 to set
SCLKR[2:0] based on the system clock frequency.
CAUTION: If the correct value for SCLKR[2:0] is not selected from the table, the
pulse timer may run too fast and cause damage to the device.
The system clock period is multiplied by the clock scaling value to
generate a 83.3-ns to 125-ns scaled clock. This scaled clock is used to
run the charge pump submodule and the next functional block of the
timing control.
NOTE:
The minimum specified system clock frequency for program and erase
operations is 8.0 MHz. The CMFR does not have any means to monitor
the system clock frequency and cannot prevent program or erase
operation at frequencies below 8.0 MHz. Attempting to program or erase
the CMFR at system clock frequencies lower than 8.0 MHz does not
damage the device if the maximum pulse times and total times are not
exceeded. While some bits in the CMFR array may change state if
programmed or erased at system clock frequencies below 8.0 MHz, the
full program or erase transition is not assured.
Technical Data
198
Non-Volatile Memory FLASH (CMFR)
For More Information On This Product,
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MMC2107 – Rev. 2.0
MOTOROLA