MMC2107 Datasheet, PDF (422/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
18.8.5.3 QADC Control Register 2
Control register 2 (QACR2) is the mode control register for the operation
of queue 2. Software specifies the queue operating mode of queue 2
and may enable a completion and/or a pause interrupt. Most of the bits
are typically written once when the software initializes the QADC and not
changed afterward.
Stop mode resets the register ($007f)
Address: 0x00ca_000e and 0x00ca_000f
Bit 15
14
13
12
11
10
9
Read:
0
CIE2
PIE2
MQ212 MQ211 MQ210 MQ29
Write:
SSE2
Reset: 0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Read:
RESUME
Write:
BQ26
BQ25
BQ24
BQ23
BQ22
BQ21
Reset: 0
1
1
1
1
1
1
Figure 18-10. QADC Control Register 2 (QACR2)
Bit 8
MQ28
0
Bit 0
BQ20
1
Read: Anytime
Write: Anytime except stop mode
CIE2 — Queue 2 Completion Software Interrupt Enable Bit
CIE2 enables an interrupt upon completion of queue 2. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 2.
1 = Enable an interrupt after an end-of-conversion for queue 2.
0 = Disable the queue completion interrupt associated with
queue 2.
Technical Data
422
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA