MMC2107 Datasheet, PDF (559/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
OnCE resource to be accessed as a DR during the TAP controller
capture-DR, shift-DR and update-DR states.
OnCE COMMAND REGISTER
TDI
TCLK
ISBKPT
ISTRACE
ISDR
OnCE
DECODER
OnCE TAP
CONTROLLER
TMS
OnCE STATUS
AND CONTROL
REGISTERS
TDO
REGISTER
READ
REGISTER
WRITE
CPU
CONTROL/
STATUS
Figure 21-7. OnCE Controller and Serial Interface
21.14.3 OnCE Interface Signals
The following paragraphs describe the OnCE interface signals to other
internal blocks associated with the OnCE controller. These signals are
not available externally, and descriptions are provided to improve
understanding of OnCE operation.
21.14.3.1 Internal Debug Request Input (IDR)
The internal debug request input is a hardware signal which is used in
some implementations to force an immediate debug request to the CPU.
If present and enabled, it functions in an identical manner to the control
function provided by the DR control bit in the OCR. This input is
maskable by a control bit in the OCR.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
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Technical Data
559