MMC2107 Datasheet, PDF (165/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
Memory Map and Registers
7.7.2.7 Fast Interrupt Enable Register
The read/write, 32-bit fast interrupt enable register (FIER) enables any
current pending interrupts which are assigned at each priority level as a
fast interrupt source. Enabling an interrupt source which has an asserted
request causes that interrupt to become pending, and a request to the
M•CORE processor is asserted if not already outstanding.
Address: 0x00c5_0018 through 0x00c5_001b
Bit 31
30
29
28
27
26
25
Read:
FIE31
Write:
FIE30
FIE29
FIE28
FIE27
FIE26
FIE25
Reset: 0
0
0
0
0
0
0
Bit 23
22
21
20
19
18
17
Read:
FIE23
Write:
FIE22
FIE21
FIE20
FIE19
FIE18
FIE17
Reset: 0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Read:
FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9
Write:
Reset: 0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Read:
FIE7
FIE6
FIE5
FIE4
FIE3
FIE2
FIE1
Write:
Reset: 0
0
0
0
0
0
0
Figure 7-9. Fast Interrupt Enable Register (FIER)
Bit 24
FIE24
0
Bit 16
FIE16
0
Bit 8
FIE8
0
Bit 0
FIE0
0
FIE[31:0] — Fast Interrupt Enable Field
The read/write FIE[31:0] field enables interrupt requests from sources
at the corresponding priority level as fast interrupts. Reset clears
FIE[31:0].
1 = Fast interrupt enabled
0 = Fast interrupt disabled
MMC2107 – Rev. 2.0
MOTOROLA
Interrupt Controller Module
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Technical Data
165