MMC2107 Datasheet, PDF (355/618 Pages) –

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
Transmitter
16.11.3 Break Frames
Setting the SBK bit in SCICR2 loads the transmit shift register with a
break frame. A break frame contains all logic 0s and has no start, stop,
or parity bit. Break frame length depends on the M bit in the SCICR1
register. As long as SBK is set, the SCI continuously loads break frames
into the transmit shift register. After SBK is clear, the transmit shift
register finishes transmitting the last break frame and then transmits at
least one logic 1. The automatic logic 1 at the end of a break frame
guarantees the recognition of the next start bit.
The SCI recognizes a break frame when a start bit is followed by eight
or nine 0 data bits and a 0 where the stop bit should be. Receiving a
break frame has these effects on SCI registers:
• Sets the FE flag
• Sets the RDRF flag
• Clears the SCIDRH and SCIDRL
• May set the OR flag, NF flag, PE flag, or the RAF flag
16.11.4 Idle Frames
An idle frame contains all logic 1s and has no start, stop, or parity bit. Idle
frame length depends on the M bit in the SCICR1 register. The preamble
is a synchronizing idle frame that begins the first transmission after
writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the TXD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle frame to be sent
after the frame currently being transmitted.
NOTE:
When queueing an idle frame, return the TE bit to logic 1 before the stop
bit of the current frame shifts out to the TXD pin. Setting TE after the stop
bit appears on TXD causes data previously written to SCIDRH and
SCIDRL to be lost toggle TE for a queued idle frame while the TDRE flag
is set and immediately before writing new data to SCIDRH and SCIDRL.
MMC2107 – Rev. 2.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
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Technical Data
355