MMC2107 Datasheet, PDF (578/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Reserved bits represent the internal processor state. Restore these bits
to their original value after a debug session is completed, for example,
when a OnCE command is issued with the GO and EX bits set and not
ignored. Set these bits to 1s while instructions are executed during a
debug session.
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
RSVD
14
RSVD
13
RSVD
12
RSVD
11
RSVD
10
RSVD
9
RSVD
Bit 7
6
5
4
3
2
1
FDB
SZ1
SZ0
TC2
TC1
TC0
RSVD
0
0
0
0
0
0
Figure 21-14. Control State Register (CTL)
Bit 8
FFY
0
Bit 0
RSVD
FFY — Feed Forward Y Operand Bit
This control bit is used to force the content of the WBBR to be used
as the Y operand value of the first instruction to be executed following
an update of the CPUSCR. This gives the debug firmware the
capability of updating processor registers by initializing the WBBR
with the desired value, setting the FFY bit, and executing a MOV
instruction to the desired register.
FDB — Force Debug Enable Mode Bit
Setting this control bit places the processor in debug enable mode. In
debug enable mode, execution of the BKPT instruction as well as
recognition of the BRKRQ input causes the processor to enter debug
mode, as if the DBGRQ input had been asserted.
SZ1 and SZ0 — Prefetch Size Field
This control field is used to drive the CPU SIZ1 and SIZ0 outputs on
the first instruction pre-fetch caused by issuing a OnCE command
with the GO bit set and not ignored. It should be set to indicate a 16-bit
size, for example, 0b10. This field should be restored to its original
value after a debug session is completed, for example, when a OnCE
command is issued with the GO and EX bits set and not ignored.
Technical Data
578
JTAG Test Access Port and OnCE
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
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