MMC2107 Datasheet, PDF (577/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
21.14.12.1 Program Counter Register
The program counter register (PC) is a 32-bit latch that stores the value
in the CPU program counter when the device enters debug mode. The
CPU PC is affected by operations performed during debug mode and
must be restored by the external command controller when the CPU
returns to normal mode.
21.14.12.2 Instruction Register
The instruction register (IR) provides a mechanism for controlling the
debug session. The IR allows the debug control block to execute
selected instructions; the debug control module provides single-step
capability.
When scan-out begins, the IR contains the opcode of the next instruction
to be executed at the time debug mode was entered. This opcode must
be saved in order to resume normal execution at the point debug mode
was entered.
On scan-in, the IR can be filled with an opcode selected by debug control
software in preparation for exiting debug mode. Selecting appropriate
instructions allows a user to examine or change memory locations and
processor registers.
Once the debug session is complete and normal processing is to be
resumed, the IR can be loaded with the value originally scanned out.
21.14.12.3 Control State Register
The control state register (CTL) is used to set control values when debug
mode is exited. On scan-in, this register is used to control specific
aspects of the CPU. Certain bits reflect internal processor status and
should be restored to their original values.
The CTL register is a 16-bit latch that stores the value of certain internal
CPU state variables before debug mode is entered. This register is
affected by the operations performed during the debug session and
should be restored by the external command controller when returning
to normal mode. In addition to saved internal state variables, the bits are
used by emulation firmware to control the debug process.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
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Technical Data
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