MMC2107 Datasheet, PDF (223/618 Pages) –

Freescale Semiconductor, Inc.
Clock Module
Modes of Operation
10.4 Modes of Operation
The clock module can be operated in normal PLL mode, 1:1 PLL mode,
or external clock mode.
10.4.1 Normal PLL Mode
In normal PLL mode, the PLL is fully programmable. It can synthesize
frequencies ranging from 2x to 9x the reference frequency and has a
post divider capable of reducing this synthesized frequency without
disturbing the PLL. The PLL reference can be either a crystal oscillator
or an external clock.
10.4.2 1:1 PLL Mode
In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external
clock input reference frequency. The post divider is not active.
10.4.3 External Clock Mode
In external clock mode, the PLL is bypassed, and the external clock is
applied to EXTAL.
10.4.4 Low-Power Options
During wakeup from a low-power mode, the FLASH clock always clocks
through at least 16 cycles before the core clocks are enabled. This
allows the FLASH module time to recover from the low-power mode, and
software can immediately resume fetching instructions from the flash
memory.
10.4.4.1 Wait and Doze Modes
In wait and doze modes, the system clocks to the peripherals are
enabled, and the clocks to the CPU, FLASH, and random-access
memory (RAM) are stopped. Each module can disable the module
clocks locally at the module level.
MMC2107 – Rev. 2.0
MOTOROLA
Clock Module
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Technical Data
223