MMC2107 Datasheet, PDF (423/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
PIE2 — Queue 2 Pause Software Interrupt Enable Bit
PIE2 enables an interrupt when queue 2 enters the pause state. The
interrupt request is initiated when conversion is complete for a CCW
that has the pause bit set.
1 = Enable an interrupt after an end-of-conversion for queue 2
which has the pause bit set.
0 = Disable the pause interrupt associated with queue 2.
SSE2 — Queue 2 Single-Scan Enable Bit
SSE2 enables a single-scan of queue 2 to start after a trigger event
occurs. The SSE2 bit may be set to a 1 during the same write cycle
when the MQ2 bits are set for one of the single-scan queue operating
modes. The single-scan enable bit can be written as a 1 or a 0, but is
always read as a 0, unless a test mode is selected. The SSE2 bit
enables a trigger event to initiate queue execution for any single-scan
operation on queue 2. The QADC clears the SSE2 bit when the
single-scan is complete.
1 = Accept a trigger event to start queue 2 in a single-scan mode.
0 = Trigger events are not accepted for single-scan modes.
MQ2[12:8] — Queue 2 Operating Mode Field
The MQ2 field selects the queue operating mode for queue 2.
Table 18-6 shows the bits in the MQ2 field which enable different
queue 2 operating modes.
Table 18-6. Queue 2 Operating Modes
MQ2[12:8]
00000
00001
00010
00011
00100
00101
00110
00111
01000
Operating Modes
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2⁷
Interval timer single-scan mode: time = QCLK period x 2⁸
Interval timer single-scan mode: time = QCLK period x 2⁹
Interval timer single-scan mode: time = QCLK period x 2¹⁰
Interval timer single-scan mode: time = QCLK period x 2¹¹
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
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Technical Data
423