MMC2107 Datasheet, PDF (217/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
Functional Description
T3
S2
T1
T2
T6
S3
T4
RESET
S1
S4
T7
T8
T5
T9
S5
Figure 9-10. Erase State Diagram
Table 9-10 Erase Interlock State Descriptions
State
Mode
Next
State
Transition Requirement
Normal operation: Normal array reads and
S1
register accesses. Block protect information
and pulse-width timing control can be
modified.
S2 T2 Write ERASE = 1 and SES = 1
Erase hardware interlock write: Normal read
operation. CMFR accepts erase hardware
interlock write to any array location. Normal
register access (except CMFRMCR).
S2 CMFRCTL write cannot set EHV. Register
write (except CMFRMCR) is not erase
hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3.
S1 T1 Write SES = 0 or a master reset
Hardware interlock: Write to any array
location is erase interlock write. Register
write other than CMFRMCR is not erase
S3 T3 hardware interlock write; CMFR remains in
S2. CMFRMCR write causes transition to
S3; NVM fuses cleared during high-voltage
pulse
MMC2107 – Rev. 2.0
MOTOROLA
Non-Volatile Memory FLASH (CMFR)
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Technical Data
217