MMC2107 Datasheet, PDF (449/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Functional Description
18.9.3.5 Digital-to-Analog Converter (DAC) Array
The digital-to-analog converter (DAC) array consists of binary-weighted
capacitors and a resistor-divider chain. The reference voltages, VRH
and VRL, are used by the DAC to perform ratiometric conversions. The
DAC also converts the following three internal channels:
• V_RH — reference voltage high
• V_RL — reference voltage low
• (V_RH–V_RL)/2 — reference voltage
The DAC array serves to provide a mechanism for the successive
approximation A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to
the least significant bit (LSB). The switching sequence is controlled by
the comparator and SAR logic. The sample capacitor samples and holds
the voltage to be converted.
18.9.3.6 Comparator
During the approximation process, the comparator senses whether the
digitally selected arrangement of the DAC array produces a voltage level
higher or lower than the sampled input. The comparator output feeds
into the SAR which accumulates the A/D conversion result sequentially,
beginning with the MSB.
18.9.3.7 Bias
The bias circuit is controlled by the STOP signal to power-up and
power-down all the analog circuits.
18.9.3.8 Successive-Approximation Register
The input of the SAR is connected to the comparator output. The SAR
sequentially receives the conversion value one bit at a time, starting with
the MSB. After accumulating the 10 bits of the conversion result, the
SAR data is transferred to the appropriate result location, where it may
be read from the IPbus by user software.
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
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Technical Data
449