MMC2107 Datasheet, PDF (314/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.7.14 Timer Channel Registers
Address: TIMC0H — 0x00ce_0010/0x00cf_0010
TIMC1H — 0x00ce_0012/0x00cf_0012
TIMC2H — 0x00ce_0014/0x00cf_0014
TIMC3H — 0x00ce_0016/0x00cf_0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Figure 15-17. Timer Channel [0:3] Register High (TIMCxH)
Address: TIMC0L — 0x00ce_0011/0x00cf_0011
TIMC1L — 0x00ce_0013/0x00cf_0013
TIMC2L — 0x00ce_0015/0x00cf_0015
TIMC3L — 0x00ce_0017/0x00cf_0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 15-18. Timer Channel [0:3] Register Low (TIMCxL)
Read: Anytime
Write: Output compare channel, anytime; input capture channel, no
effect
When a channel is configured for input capture (IOSx = 0), the timer
channel registers latch the value of the free-running counter when a
defined transition occurs on the corresponding input capture pin.
When a channel is configured for output compare (IOSx = 1), the timer
channel registers contain the output compare value.
To ensure coherent reading of the timer counter, such that a timer
rollover does not occur between back-to-back 8-bit reads, it is
recommended that only half-word (16-bit) accesses be used.
Technical Data
314
Timer Modules (TIM1 and TIM2)
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MMC2107 – Rev. 2.0
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