MMC2107 Datasheet, PDF (158/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
ME — Mask Enable Bit
The read/write ME bit enables interrupt masking. Reset clears ME.
1 = Interrupt masking enabled
0 = Interrupt masking disabled
MFI — Mask Fast Interrupts Bit
The read/write MFI bit enables masking of fast interrupt requests.
Reset clears MFI.
1 = Fast interrupt requests masked by MASK value. All normal
interrupt requests are masked.
0 = Fast interrupt requests are not masked regardless of the MASK
value. The MASK only applies to normal interrupts. Reset
clears MFI.
MASK[4:0] — Interrupt Mask Field
The read/write MASK[4:0] field determines which interrupt priority
levels are masked. When the ME bit is set, all pending interrupt
requests at priority levels at and below the current MASK value are
masked. To mask all normal interrupts without masking any fast
interrupts, set the MASK value to 31 with the MFI bit cleared. See
Table 7-2. Reset clears MASK[4:0].
Table 7-2. MASK Encoding
MASK[4:0]
Decimal
Binary
0
00000
1
00001
2
00010
3
00011
•
•
•
•
•
•
31
11111
Masked Priority
Levels
0
1–0
2–0
3–0
•
•
•
31–0
Technical Data
158
Interrupt Controller Module
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MMC2107 – Rev. 2.0
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