MMC2107 Datasheet, PDF (396/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
If the mode fault error occurs in bidirectional mode, the DDRSP bit of the
SISO pin is not affected, since it is a general-purpose I/O pin.
17.8.8 Low-Power Mode Options
This subsection describes the low-power mode options.
17.8.8.1 Run Mode
Clearing the SPE bit in SPICR1 puts the SPI in a disabled, low-power
state. SPI registers are accessible, but SPI clocks are disabled.
17.8.8.2 Doze Mode
SPI operation in doze mode depends on the state of the SPISDOZ bit in
SPICR2.
• If SPISDOZ is clear, the SPI operates normally in doze mode.
• If SPISDOZ is set, the SPI clock stops, and the SPI enters a
low-power state in doze mode.
– Any master transmission in progress stops at doze mode entry
and resumes at doze mode exit.
– Any slave transmission in progress continues if a master
continues to drive the slave SCK pin. The slave stays
synchronized to the master SCK clock.
NOTE:
Although the slave shift register can receive MOSI data, it cannot
transfer data to SPIDR or set the SPIF flag in doze or stop mode. If the
slave enters doze mode in an idle state and exits doze mode in an idle
state, SPIF remains clear and no transfer to SPIDR occurs.
17.8.8.3 Stop Mode
SPI operation in stop mode is the same as in doze mode with the
SPISDOZ bit set.
Technical Data
396
Serial Peripheral Interface Module (SPI)
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MMC2107 – Rev. 2.0
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