MMC2107 Datasheet, PDF (541/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Instruction Shift Register
21.5 Instruction Shift Register
The MMC2107 top-level TAP module uses a 4-bit instruction shift
register with no parity. This register transfers its value to a parallel hold
register and applies an instruction on the falling edge of TCLK when the
TAP state machine is in the update-IR state. To load the instructions into
the shift portion of the register, place the serial data on the TDI pin prior
to each rising edge of TCLK. The MSB of the instruction shift register is
the bit closest to the TDI pin and the LSB is the bit closest to the TDO pin.
Table 21-1 lists the instructions supported along with their opcodes,
IR3–IR0. The last three instructions in the table are reserved for
manufacturing purposes only.
Unused opcodes are currently decoded to perform the BYPASS
operation, but Motorola reserves the right to change their decodings in
the future.
21.5.1 EXTEST Instruction
The external test instruction (EXTEST) selects the boundary-scan
register. The EXTEST instruction forces all output pins and bidirectional
pins configured as outputs to the preloaded fixed values (with the
SAMPLE/PRELOAD instruction) and held in the boundary-scan update
registers. The EXTEST instruction can also configure the direction of
bidirectional pins and establish high-impedance states on some pins.
EXTEST also asserts internal reset for the MMC2107 system logic to
force a predictable internal state while performing external boundary
scan operations.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
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Technical Data
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