MMC2107 Datasheet, PDF (579/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
TC — Prefetch Transfer Code
This control field is used to drive the CPU TC2–TC0 outputs on the
first instruction pre-fetch caused by issuing a OnCE command with
the GO bit set and not ignored. It should typically be set to indicate a
supervisor instruction access, for example, 0b110. This field should
be restored to its original value after a debug session is completed,
for example, when a OnCE command is issued with the GO and EX
bits set and not ignored.
21.14.12.4 Writeback Bus Register
The writeback bus register (WBBR) is a means of passing operand
information between the CPU and the external command controller.
Whenever the external command controller needs to read the contents
of a register or memory location, it forces the device to execute an
instruction that brings that information to WBBR.
For example, to read the content of processor register r0, a MOV r0,r0
instruction is executed, and the result value of the instruction is latched
into the WBBR. The contents of WBBR can then be delivered serially to
the external command controller.
To update a processor resource, this register is initialized with a data
value to be written, and a MOV instruction is executed which uses this
value as a write-back data value. The FFY bit in the CTL register forces
the value of the WBBR to be substituted for the normal source value of
a MOV instruction, thus allowing updates to processor registers to be
performed.
21.14.12.5 Processor Status Register
The processor status register (PSR) is a 32-bit latch used to read or write
the M•CORE processor status register. Whenever the external
command controller needs to save or modify the contents of the
M•CORE processor status register, the PSR is used. This register is
affected by the operations performed in debug mode and must be
restored by the external command controller when returning to normal
mode.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
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Technical Data
579