MMC2107 Datasheet, PDF (59/618 Pages) –

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address
0x00c0_002c
0x00c0_002d
↓
0x00c0_002f
0x00c0_0030
0x00c0_0031
0x00c0_0032
↓
0x00c0_003f
0x00c0_0040
↓
0x00c0_ffff
Register Name
Port I Clear Output
Data Register (CLRI)
See page 254.
Read:
Write:
Reset:
Bit 7
0
CLRI7
0
Bit 7
6
0
CLRI6
0
6
5
0
CLRI5
0
5
Bit Number
4
3
0
0
CLRI4 CLRI3
0
0
4
3
2
0
CLRI2
0
2
1
0
CLRI1
0
1
Bit 0
0
CLRI0
0
Bit 0
Reserved
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7
6
5
4
3
2
1
Bit 0
Port C/D Pin Read:
0
0
0
0
0
0
0
Assignment Register
(PCDPAR)
Write:
PCDPA
See page 255. Reset: See note
0
0
0
0
0
0
0
Note: Reset state determined during reset configuration. PCDPA = 1 except in single-chip
mode or when an external boot device is selected with a 16-bit port size in master mode.
Bit 7
6
5
4
3
2
1
Bit 0
Port E Pin Read:
Assignment Register
(PEPAR)
Write:
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
See page 256. Reset: Reset state determined during reset configuration as shown in Table 11-2. PEPAR Reset Values.
Bit 7
6
5
4
3
2
1
Bit 0
Reserved
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7
6
5
4
3
2
1
Bit 0
Reserved
Ports register space (block of 0x00c0_0000 through 0x00c0_oo3f) is mirrored/repeated.
P = Current pin state
U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 6 of 34)
MMC2107 – Rev. 2.0
MOTOROLA
System Memory Map
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Technical Data
59