MMC2107 Datasheet, PDF (489/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Pin Connection Considerations
CONVERSION TIME
Å  14 QCLKS
QCLK
TIME BETWEEN
TRIGGERS
CONVERSION TIME
Å  14 QCLKS
TRIG1
EOC
QS
0
8
4
8
CWP LAST
CCW0
CCW1
CCW2
CWPQ1
LAST
CCW0
CCW1
Q1 RES
R0
R1
Figure 18-47. External Positive Edge Trigger Mode Timing With Pause
A time separator is provided between the triggers and the end of
conversion (EOC). The relationship to QCLK displayed is not
guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the
associated queue is inactive. Another way to view CWPQ1(2) is that
these registers update when EOC triggers the result register to be
written.
In the case with the pause bit set (CCW0), CWP does not increment until
triggered. In the case with the pause bit clear (CCW1), the CWP
increments with the EOC.
The conversion results Q1 Res(x) show the result associated with
CCW(x). So that R0 represents the result associated with CCW0.
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
489