MMC2107 Datasheet, PDF (310/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.7.11 Timer System Control Register 2
Address: TIM1 — 0x00ce_000d
TIM2 — 0x00cf_000d
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOI
Write:
0
PUPT RDPT TCRE PR2
PR1
PR0
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-14. Timer System Control Register 2 (TIMSCR2)
Read: Anytime
Write: Anytime
TOI — Timer Overflow Interrupt Enable Bit
TOI enables timer overflow interrupt requests.
1 = Overflow interrupt requests enabled
0 = Overflow interrupt requests disabled
PUPT — Timer Pullup Enable Bit
PUPT enables pullup resistors on the timer ports when the ports are
configured as inputs.
1 = Pullup resistors enabled
0 = Pullup resistors disabled
RDPT — Timer Drive Reduction Bit
RDPT reduces the output driver size.
1 = Output drive reduction enabled
0 = Output drive reduction disabled
TCRE — Timer Counter Reset Enable Bit
TCRE enables a counter reset after a channel 3 compare.
1 = Counter reset enabled
0 = Counter reset disabled
NOTE: When the timer channel 3 registers contain $0000 and TCRE is set, the
timer counter registers remain at $0000 all the time.
Technical Data
310
Timer Modules (TIM1 and TIM2)
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MMC2107 – Rev. 2.0
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